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AD9520-1/PCBZ データシート(PDF) 12 Page - Analog Devices |
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AD9520-1/PCBZ データシート(HTML) 12 Page - Analog Devices |
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12 / 80 page  AD9520-1 Data Sheet Rev. B | Page 12 of 80 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R divider = 1 LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration BW = 200 kHz to 5 MHz 77 fs rms Integration BW = 200 kHz to 10 MHz 109 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration BW = 200 kHz to 5 MHz 114 fs rms Integration BW = 200 kHz to 10 MHz 163 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration BW = 200 kHz to 5 MHz 176 fs rms Integration BW = 200 kHz to 10 MHz 259 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; measured at rising edge of clock signal CLK = 622.08 MHz 46 fs rms Integration bandwidth = 12 kHz to 20 MHz Any LVPECL Output = 622.08 MHz Divide Ratio = 1 CLK = 622.08 MHz 64 fs rms Integration bandwidth = 12 kHz to 20 MHz Any LVPECL Output = 155.52 MHz Divide Ratio = 4 CLK = 1000 MHz 223 fs rms Calculated from SNR of ADC method Any LVPECL Output = 100 MHz Broadband jitter Divide Ratio = 10 CLK = 500 MHz 209 fs rms Calculated from SNR of ADC method Any LVPECL Output = 100 MHz Broadband jitter Divide Ratio = 5 CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO CLK = 200 MHz 325 fs rms Calculated from SNR of ADC method Any CMOS Output Pair = 100 MHz Broadband jitter Divide Ratio = 2 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz; Channel Divider = 2; Duty-Cycle Correction = Off 230 fs rms Calculated from SNR of ADC method (broadband jitter) CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On 215 fs rms Calculated from SNR of ADC method (broadband jitter) CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off 326 fs rms Calculated from SNR of ADC method (broadband jitter) CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz; Channel Divider = 8; Duty-Cycle Correction = Off 362 fs rms Calculated from SNR of ADC method (broadband jitter) |
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