GPR25L005E datasheet(12/38 Pages) GENERALPLUS

12 / 38 page

GPR25L005E

Proprietary & Confidential

Aug. 08, 2011

Version: 1.0

9. COMMAND DESCRIPTION

9.1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable

Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and

WRSR, which are intended to change the device content, should

be set every time after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→

sending WREN instruction code→ CS# goes high. (see Figure 11)

9.2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable

Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→

sending WRDI instruction code→ CS# goes high. (see Figure 12)

The WEL bit is reset by following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

9.3. Read Identification (RDID)

RDID instruction is for reading the manufacturer ID of 1-byte and

followed by Device ID of 2-byte. The Manufacturer ID is C2(hex),

the memory type ID is 20(hex) as the first-byte device ID, and the

individual device ID of second-byte ID is as followings: 10(hex) for

GPR25L005E.

The sequence of issuing RDID instruction is: CS# goes

low→sending RDID instruction code→24-bits ID data out on

SO→to end RDID operation can use CS# to high at any time

during data out. (see Figure. 13)

While Program/Erase operation is in progress, it will not decode

the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When

CS# goes high, the device is at standby stage.

9.4. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The

Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously.

It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status

The sequence of issuing RDSR instruction is: CS# goes

low→sending RDSR instruction code→Status Register data out

on SO (see Figure. 14)

The definition of the status register bits is as below:

WIP bit.

The Write in Progress (WIP) bit, a volatile bit, indicates

whether the device is busy in program/erase/write status register

progress. When WIP bit sets to 1, which means the device is

busy in program/erase/write status register progress. When WIP

bit sets to 0, which means the device is not in progress of

program/erase/write status register cycle.

WEL bit.

The Write Enable Latch (WEL) bit, a volatile bit,

indicates whether the device is set to internal write enable latch.

When WEL bit sets to 1, which means the internal write enable

latch is set, the device can accept program/erase/write status

internal write enable latch; the device will not accept

program/erase/write status register instruction.

BP1, BP0 bits.

The Block Protect (BP1, BP0) bits, non-volatile

bits, indicate the protected area(as defined in table 1) of the

device to against the program/erase instruction without hardware

protection mode being set. To write the Block Protect (BP1, BP0)

bits requires the Write Status Register (WRSR) instruction to be

executed. Those bits define the protected area of the memory to

against Page Program (PP), Sector Erase (SE), Block Erase (BE)

and Chip Erase(CE) instructions (only if all Block Protect bits set

to 0, the CE instruction can be executed)

SRWD bit.

The Status Register Write Disable (SRWD) bit,

non-volatile bit, is operated together with Write Protection (WP#)

pin for providing hardware protection mode. The hardware

protection mode requires SRWD sets to 1 and WP# pin signal is

low stage. In the hardware protection mode, the Write Status

and the SRWD bit and Block Protect bits (BP1, BP0) are read

only.

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