GPR25L12805F datasheet(29/58 Pages) GENERALPLUS

部品番号	GPR25L12805F

部品情報	128M-bit [x 1/x 2/x 4] CMOS Serial Flash

PDF	58 Pages

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メーカー	GENERALPLUS [Generalplus Technology Inc.]

ホームページ	http://www.generalplus.com

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GPR25L12805F

Proprietary & Confidential

Nov. 23, 2017

Version: 1.1

Fast Boot Register (FBR)

Bits

Description

Bit Status

Default State

Type

31 to 4

FBSA (FastBoot Start Address)

8 bytes boundary address for

the start of boot code access.

FFFFFFF

Non- Volatile

2 to 1

FBSD (FastBoot Start Delay

Cycle)

00: 6 delay cycles

01: 8 delay cycles

10: 10 delay cycles

11: 12 delay cycles

Non- Volatile

FBE (FastBoot Enable)

0=FastBoot is enabled.

1=FastBoot is not enabled.

Non- Volatile

Note: If FBSD = 11, the maximum clock frequency is 133 MHz

If FBSD = 10, the maximum clock frequency is 104 MHz

If FBSD = 01, the maximum clock frequency is 84 MHz

If FBSD = 00, the maximum clock frequency is 70 MHz

Figure 39. Fast Boot Sequence (QE bit =0)

Figure 40. Fast Boot Sequence (QE bit =1)

Figure 41. Read Fast Boot Register (RDFBR) Sequence

Figure 42. Write Fast Boot Register (WRFBR) Sequence

Figure 43. Erase Fast Boot Register (ESFBR) Sequence

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