GPR25L12805F datasheet(31/58 Pages) GENERALPLUS

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GPR25L12805F

Proprietary & Confidential

Nov. 23, 2017

Version: 1.1

Chip Select (CS#) goes high.

The Write in Progress (WIP) bit still

can be checked while the Block Erase cycle is in progress.

The

WIP sets during the tBE timing, and clears when Block Erase

Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

If the Block is protected by BP bits (WPSEL=0; Block Protect

Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),

the Block Erase (BE) instruction will not be executed on the block.

Figure 48. Block Erase (BE) Sequence (SPI Mode)

Figure 49. Block Erase (BE) Sequence (QPI Mode)

9.24. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the

whole chip to be "1".

A Write Enable (WREN) instruction must be

executed to set the Write Enable Latch (WEL) bit before sending

the Chip Erase (CE).

The CS# must go high exactly at the byte

boundary, otherwise the instruction will be rejected and not

executed.

The sequence of issuing CE instruction is: CS# goes low→sending

CE instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept

by this instruction.

The SIO[3:1] are don't care when during SPI

mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as

Chip Select (CS#) goes high.

The Write in Progress (WIP) bit still

can be checked while the Chip Erase cycle is in progress.

The

WIP sets during the tCE timing, and clears when Chip Erase Cycle

is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block protect (BP) Mode" (WPSEL=0).

The Chip Erase(CE) instruction will not be executed, if one (or

more) sector is protected by BP3-BP0 bits.

It will be only

executed when BP3-BP0 all set to "0".

When the chip is under "Advances Sector Protect Mode"

(WPSEL=1).

The Chip Erase (CE) instruction will be executed on

unprotected block.

The protected Block will be skipped.

If one

(or more) 4K byte sector was protected in top or bottom 64K byte

block, the protected block will also skip the chip erase command.

Figure 50. Chip Erase (CE) Sequence (SPI Mode)

Figure 51. Chip Erase (CE) Sequence (QPI Mode)

9.25. Page Program (PP)

The Page Program (PP) instruction is for programming the

memory to be "0".

A Write Enable (WREN) instruction must be

executed to set the Write Enable Latch (WEL) bit before sending

the Page Program (PP).

The device programs only the last 256

data bytes sent to the device.

If the entire 256 data bytes are

going to be programmed, A7- A0 (The eight least significant

address bits) should be set to 0.

If the eight least significant

address bits (A7-A0) are not all 0, all transmitted data going

beyond the end of the current page are programmed from the start

address of the same page (from the address A7-A0 are all 0).

more than 256 bytes are sent to the device, the data of the last

256-byte is programmed at the requested page and previous data

will be disregarded.

If less than 256 bytes are sent to the device,

the data is programmed at the requested address of the page

without effect on other address of the same page.

The sequence of issuing PP instruction

is: CS# goes low→

sending PP instruction code→ 3-byte address on SI→ at least

byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program

cycle; The CS# must go high exactly at the byte boundary( the

latest eighth bit of data being latched in), otherwise the instruction

will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon

as Chip Select (CS#) goes high.

The Write in Progress (WIP) bit

still can be checked while the Page Program cycle is in progress.

The WIP sets during the tPP timing, and clears when Page

Program Cycle is completed, and the Write Enable Latch (WEL) bit

is cleared.

If the Block is protected by BP bits (WPSEL=0; Block

Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode) the Page Program (PP) instruction will not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept

by this instruction.

The SIO[3:1] are don't care when during SPI

mode.

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