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GD25LB128DSJS データシート(PDF) 27 Page - GigaDevice Semiconductor (Beijing) Inc.

部品番号 GD25LB128DSJS
部品情報  1.8V Uniform Sector Dual and Quad Serial Flash
PDF  75 Pages
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メーカー  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
ホームページ  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25LB128DSJS データシート(HTML) 27 Page - GigaDevice Semiconductor (Beijing) Inc.

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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LB128D
27
7.11.
Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a
“Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, and
each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Quad I/O Fast Read with
“Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the
“Continuous Read
Mode
” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure12a. If the
“Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the
next command requires the first EBH command code, thus returning to normal operation. A
“Continuous Read Mode” Reset
command can be used to reset (M5-4) before issuing normal command.
Figure12. Quad I/O Fast Read Sequence Diagram (M5-4
≠ (1, 0))
Figure12a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
Command
0
1
2
3
4
5
6
7
EBH
CS#
SCLK
IO0
IO1
8
9 10 11 12 13 14 15
4
0
4
0
4
0
4
0
16 17 18 19 20 21 22 23
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
A23-16 A15-8 A7-0
M7-0
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
IO2
IO3
4
5
6
7
Dummy
Byte1 Byte2
0
1
2
3
4
5
6
7
CS#
SCLK
8
9 10 11 12 13 14 15
IO0
IO1
IO2
IO3
4
0
4
0
5
1
5
1
6
2
6
2
7
3
7
3
4
0
4
0
5
1
5
1
6
2
6
2
7
3
7
3
4
0
4
0
5
1
5
1
6
2
6
2
7
3
7
3
4
5
6
7
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1 Byte2



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