Data Sheet

ADF41513

Rev. 0 | Page 7 of 30

PIN CONFIGURATION AND FUNCTION DESCRIPTION

2

1

3

4

5

6

18

17

16

15

14

13

GND

CE

CLK

DATA

LE

MUXOUT

ADF41513

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST

BE CONNECTED TO GND.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Ground Pin.

2, 3

PFD and Up and Down Digital Driver Power Supply. Pin 2 and Pin 3 can be tied together. With Pin 2 and Pin 3 tied

4

Complementary Input to the RF Prescaler. In single-ended mode, decouple this pin to the ground plane with a

small bypass capacitor, typically 100 pF.

5

Input to the RF Prescaler. AC-couple this signal to the external VCO.

6

100 nF, and 100 pF.

7

100 pF.

8

10 µF, 1 µF, and 100 nF. Pin 8 powers the internal low dropout (LDO) regulator for the reference divider.

9

1 µF, and 100 nF. This pin powers the internal LDO regulator for the Σ-Δ modulator.

10

Reference Input. The reference can accept either a single-ended CMOS (dc-coupled) or single-ended sine wave

(ac-coupled). The single-ended input has a nominal threshold of 1 V and a dc equivalent input resistance of 20 kΩ.

11

DLD

Digital Lock Detect Pin. A logic high on this pin indicates PLL lock.

12

Transmit Data Pin. Pin 12 is not used. Connect Pin 12 to GND.

13

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state

mode. Registers do not hold their values when CE is low. This pin only supports 3.3 V logic inputs.

14

CLK

Serial Clock Input. CLK clocks in the serial data to the registers. The data is latched into the 32-bit shift register on

the CLK rising edge. This input is a high impedance CMOS input.

15

DATA

Serial Data Input. The serial data is loaded most significant bit (MSB) first with the two least significant bits (LSBs) as

the control bits. This input is a high impedance CMOS input.

16

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches. Select the latch using the control bits.

17

MUXOUT

Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, the scaled reference frequency,

logic high, logic low, or register readback data to be accessed externally.

18

100 nF, and 1 nF.

19

100 nF, and 1 nF.

20

DC1

DC Bias Pin 1. Place a 1 µF capacitor in parallel with a 1 nF capacitor to ground, as close as possible to the DC1 pin.

21

DC2

DC Bias Pin 2. Place a 1 µF capacitor in parallel with a 1 nF capacitor to ground, as close as possible to the DC2 pin.

22

Charge Pump Power Supply.

23