Data Sheet

ADF41513

Rev. 0 | Page 23 of 30

REGISTER 7 (R7) MAP

Lock Detector Count (LD_COUNT)

LD_COUNT sets the initial value of the lock detect counter. See

the Lock Detector section for more information about the

operation of the lock detector.

Lock Detect Clock Select (LD_CLK_SEL)

The lock detector checks for lock on every phase comparison

cycle when LD CLK SEL = 1. Otherwise, the lock detector

speed up declaration of lock at the cost of reduced lock

indication stability during frequency changes.

SDM to N Divider Timing Adjustment (N Delay)

This control adjusts the timing between the SDM output and

the N divider. Set these bits to 0b01.

Prescaler (PS) Bias

Set these bits to 0b10.

CLK Divider Mode

Setting Register 7, Bits[19:18] = 0b10 enables a phase resync.

See the Phase Resync section for more information.

When not using phase resync, set Register 7, Bits[19:18] = 0b00.

divider value controls the timing of the phase resync pulse. See

the Phase Resync section for more information.

CLOCK 2 REGISTER (R7)

0

LC3

LC2

LC1

LS1

0

0

ND2

ND1

PB2 PB1

C2

C1

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

CLK

DIVIDER

MODE

CONTROL

BITS

DB7 DB6

0

0

0

0

.

.

.

1

1

1

1

0

0

0

0

.

.

.

1

1

1

1

...

...

...

...

...

...

...

...

...

...

...

0

0

1

1

.

.

.

0

0

1

1

0

1

0

1

.

.

.

0

1

0

1

0

1

2

3

.

.

.

4,092

4,093

4,094

4,095

CLK2 DIVIDER VALUE

C2

CLK DIV MODE

0

CLK DIVIDER OFF

1

C1

0

1

RESERVED

1

0

PHASE RESYNC

0

1

RESERVED

0

0

0

LC2

LOCK DETECTOR COUNT

0

1

LC1

0

1

1

0

0

1

LC3

0

0

0

0

0

1

0

1

1

0

0

1

1

1

1

1

2

4

8

16

32

64

128

256

LOCK DETECTOR CLOCK SELECT

LS1

0

1

PS BIAS

N DELAY

PB2

PRESCALER BIAS

0

RESERVED

1

PB1

0

1

RESERVED

1

0

RESERVED

0

1

PROGRAM THIS VALUE

ND2

SDM TO N DELAY

0

PROGRAM THIS VALUE

1

ND1

0

1

RESERVED

1

0

RESERVED

0

1

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3

DB2

DB1 DB0

C3(1)

C4(0)

C2(1) C1(1)

Figure 30. Register 7 (R7) Map