Data Sheet

ADF41513

Rev. 0 | Page 19 of 30

REGISTER 4 (R4) MAP

MOD2

Register 4, Bits[27:4] set the MOD2 value. See the N Divider

and R Counter section for more information. When using a

fixed modulus, MOD2 is ignored.

REGISTER 5 (R5) MAP

DLD Modes

Register 5, Bits[31:30] set the digital lock detect (DLD) pin

state. For normal digital lock detect, set Register 5, Bits[31:30] =

0b01. Other options tristate the pin and force a high or low

logic level, as shown in Figure 28.

CP Current Setting

Register 5, Bits[28:25] set the charge pump current. Set these

bits to the charge pump current that the loop filter is designed

for based on the application of the user. The recommended

practice is to design the loop filter for a charge pump current of

2.4 mA or 2.7 mA and then use the programmable charge pump

current to fine tune the loop filter frequency response.

LSB_P1

output frequency. To disable this frequency offset, set Register 5,

Bit 24 = 1.

Prescaler

The dual modulus prescaler (4/5 and 8/9) is set by Register 5,

Bit 23. The prescaler, at the input to the N divider, divides down

prescaler is based on a synchronous 4/5 core. The prescaler

setting affects the RF frequency and the minimum and maximum

INT value as follows:

For Integer N mode,

•

•

For fractional-N mode,

•

•

RDIV2

Register 5, Bit 22 controls the reference divide by 2 block. See

the N Divider and R Counter section for more information.

This feature can provide a 50% duty cycle signal to the PFD.

Reference Doubler

Register 5, Bit 21 controls the reference doubler block. See the

N Divider and R Counter section for more information.

R Counter

Register 5, Bits[20:16] control the R counter value. See the N

Divider and R Counter section for more information.

Phase Resync section for more information.

MOD2 REGISTER (R4)

NOTES

1. DBB MEANS DOUBLE-BUFFERED BITS.

DBB

CONTROL

BITS

24-BIT MOD2 VALUE (MOD2)

0

0

0

M1

M2

M3

M4

M5

M6

M8

M7

M9

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

0

M24

M23

...

M2

M1

MOD2 WORD

0

0

...

0

0

0

0

0

...

0

1

1

0

0

...

1

0

2

0

0

...

1

1

3

.

.

...

.

.

.

.

.

...

.

.

.

.

.

...

.

.

.

1

1

...

0

0

16,777,212

1

1

...

0

1

16,777,213

1

1

...

1

0

16,777,214

1

1

...

1

1

16,777,215

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6 DB5

DB4

DB3 DB2

DB1 DB0

C3(1)

C4(0)

C2(0) C1(0)

Figure 27. Register 4 (R4) Map