AM186ED-20KCSLASHW datasheet(32/88 Pages) AMD

32 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

WHB is asserted with AD15–AD8. WHB is the logical

OR of BHE and WR. This pin floats during reset.

WLB

Write Low Byte (output, three-state, synchronous)

WLB—This pin and WHB indicate to the system which

bytes of the data bus (upper, lower, or both) participate

in a write cycle. In 80C186 microcontroller designs, this

information is provided by BHE, AD0, and WR.

However, by using WHB and WLB, the standard

system interface logic and external address latch that

were required are eliminated.

WLB is asserted with AD7–AD0. WLB is the logical OR

of AD0 and WR. This pin floats during reset.

Write Strobe (output, synchronous)

WR—This pin indicates to the system that the data on

the bus is to be written to a memory or I/O device. WR

floats during a bus hold or reset condition. WR should

be used for DRAM write enable.

Crystal Input (input)

This pin and the X2 pin provide connections for a

fundamental mode or third-overtone, parallel-resonant

crystal used by the internal oscillator circuit. To provide

the microcontroller with an external clock source,

connect the source to the X1 pin and leave the X2 pin

unconnected.

Crystal Output (output)

This pin and the X1 pin provide connections for a

fundamental mode or third-overtone, parallel-resonant

crystal used by the internal oscillator circuit. To provide

the microcontroller with an external clock source, leave

the X2 pin unconnected and connect the source to the

X1 pin.

AM186ED-20KC/W データシート(PDF) 32 Page - Advanced Micro Devices

AM186ED-20KC/W データシート(HTML) 32 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

データシートダウンロード