AM186ED-20KCSLASHW datasheet(80/88 Pages) AMD

80 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

SWITCHING CHARACTERISTICS over Commercial operating ranges

Clock (33 MHz and 40 MHz)

Notes:

All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions

are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.

The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.

The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2

mode should be used.

Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should

used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.

Parameter

Preliminary

Unit

33 MHz

40 MHz

No.

Symbol

Description

Min

Max

Min

Max

CLKIN Requirements

tCKIN

X1 Period(a)

tCLCK

X1 Low Time (1.5 V)(a)

7.5

tCHCK

X1 High Time (1.5 V)(a)

7.5

tCKHL

X1 Fall Time (3.5 to 1.0 V)(a)

tCKLH

X1 Rise Time (1.0 to 3.5 V)(a)

CLKOUT Timing

tCLCL

CLKOUTA Period

tCLCH

CLKOUTA Low Time (CL=50 pF)

0.5tCLCL–1.5 =13.5

0.5tCLCL–1.25 =11.25

tCHCL

CLKOUTA High Time (CL=50 pF)

0.5tCLCL–1.5 =13.5

0.5tCLCL–1.25 =11.25

tCH1CH2

CLKOUTA Rise Time (1.0 to 3.5 V)

tCL2CL1

CLKOUTA Fall Time (3.5 to 1.0 V)

tLOCK

Maximum PLL Lock Time

tCICOA

X1 to CLKOUTA Skew

tCICOB

X1 to CLKOUTB Skew

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