AM652X datasheet(250/277 Pages) TI1

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250

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Detailed Description

•

MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up. MCU_MCSPI1 and

MCSPI3 may be optionally mapped to external device pads.

•

MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and

MCU_MCSPI2 are not pinned out externally.

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in the device TRM.

6.4.5.20 MMCSD

There are two MMCSD modules inside the device - MMCSD0 and MMCSD1. Each MMCSD module

includes one MMCSD Host Controller.

Each controller has the following data bus width:

•

MMCSD0 - 8-bit wide data bus

•

MMCSD1 - 4-bit wide data bus

The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10

(Secure Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with

MMCSD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs),

start/end bit insertion, and checking for syntactical correctness.

For more information, see Multimedia Card/Secure Digital (MMCSD) Interface section in the device TRM.

6.4.5.21 OSPI

The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI)

module which allows single, dual, quad or octal read and write access to external flash devices.

The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a

processor wishing to execute code directly from external flash memory), or in an indirect mode where the

module is set-up to silently perform some requested operation, signaling its completion via interrupts or

status registers. For indirect operations, data is transferred between system memory and external flash

memory via an internal SRAM which is loaded for writes and unloaded for reads by a device master at low

latency system speeds. Interrupts or status registers are used to identify the specific times at which this

SRAM should be accessed using user programmable configuration registers.

For more information, see Octal Serial Peripheral Interface (OSPI) section in the device TRM.

6.4.5.22 PCIE

The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode

PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to

8.0 Gbps per lane for serial links on backplanes and printed wiring boards.

The device includes two instantiations of PCIe subsystem named PCIE0 and PCIE1.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in the

device TRM.

6.4.5.23 SerDes

The goal of the SerDes is to convert device (SoC) parallel data into serialized data that can be output over

a high-speed electrical interface. In the opposite direction, SerDes converts high-speed serial data into

parallel data that can be processed by the device. To this end, the SerDes contains a variety of functional

blocks to handle both the external analog interface as well as the internal digital logic.

For more information, see Serializer/Deserializer (SerDes) section in the device TRM.

6.4.5.24 RTI

This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)

functionality for the device.

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