データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AM652X データシート(PDF) 251 Page - Texas Instruments

部品番号 AM652X
部品情報  Processors Silicon Revision 1.0
PDF  277 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

AM652X データシート(HTML) 251 Page - Texas Instruments

Back Button AM652X Datasheet HTML 247Page - Texas Instruments AM652X Datasheet HTML 248Page - Texas Instruments AM652X Datasheet HTML 249Page - Texas Instruments AM652X Datasheet HTML 250Page - Texas Instruments AM652X Datasheet HTML 251Page - Texas Instruments AM652X Datasheet HTML 252Page - Texas Instruments AM652X Datasheet HTML 253Page - Texas Instruments AM652X Datasheet HTML 254Page - Texas Instruments AM652X Datasheet HTML 255Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 251 / 277 page
background image
251
AM6548, AM6528, AM6546
AM6526, AM6527
www.ti.com
SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Detailed Description
Copyright © 2017–2019, Texas Instruments Incorporated
The Real Time Interrupt module provides timer functionality for operating systems and for benchmarking
code. The module incorporates several counters, which define the timebases needed for scheduling in the
operating system.
This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for
Automotive Electronics”) as well as OSEK/Time compliant operating systems.
The timers also provide the ability to benchmark certain areas of code by reading the counter contents at
the beginning and the end of the desired code range and calculating the difference between the values.
For more information, see Real Time Interrupt (RTI) Module section in the device TRM.
6.4.5.25 Timers
There are sixteen timer modules in the device.
All timers include specific functions to generate accurate tick interrupts to the operating system.
Each timer can be clocked from several different independent clocks. The selection of clock source is
made from registers in the MCU_CTRL_MMR0/CTRL_MMR0.
In the MCU domain the device provides 2 timer pins to be used as MCU Timer Capture inputs or as MCU
Timer PWM outputs. In order to provide maximum flexibility, these 2 pins may be used with any of
MCU_TIMER0 through MCU_TIMER3 instances. System level muxes are used to control the capture
source pin for each MCU_TIMER[3-0] and the MCU_TIMER[3-0] source for each MCU_TIMER_IO[1-0]
PWM output
In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer
PWM outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER11
instances. System level muxes are used to control the capture source pin for each TIMER[11-0] and the
TIMER[11-0] source for each TIMER_IO[7-0] PWM output.
For more information, see Timers section in the device TRM.
6.4.5.26 UART
The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU.
There are five UART modules in the device. All UART modules support IrDA and CIR modes when 48
MHz function clock is used. Each UART can be used for configuration and data exchange with a number
of external peripheral devices or interprocessor communication between devices.
The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a
programmable t period) to encompass the various formats of infrared encoding for remote-control
applications. The CIR logic transmits data packets based on a user-definable frame structure and packet
content.
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in
the device TRM.
6.4.5.27 USB
Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange
between a host device and a wide range of simultaneously accessible peripherals.
The device supports two USB subsystems, both instantiated in the MAIN system domain:
USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS
(USB3.0) PHY and HS/FS/LS (USB2.0) PHY
USB3SS1 is HighSpeed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS/LS
(USB2.0) PHY
For more information, see Universal Serial Bus (USB) Subsystem section in the device TRM.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com