AM652X datasheet(248/277 Pages) TI1

248 / 277 page

248

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

For more information, see Error Signaling Module (ESM) section in the device TRM.

6.4.5.11 EQEP

The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or

rotary incremental encoder to get position, direction and speed information from a rotating machine for use

in high performance motion and position control system.

For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in the device

TRM.

6.4.5.12 GPIO

The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When configured as an output, the user can write to an internal

state of the input by reading the state of an internal register.

In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in

different interrupt/event generation modes.

The device has three instances of GPIO modules. The GPIO pins are grouped into banks (16 pins per

bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated

general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to

432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and

GPIO1_[90:143] are reserved in this device, general purpose interface supports up to 242 pins.

For more information, see General-Purpose Interface (GPIO) section in the device TRM.

6.4.5.13 GPMC

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with

external memory devices like:

•

Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

•

Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash

devices

•

NAND flash

•

Pseudo-SRAM devices

For more information, see General-Purpose Memory Controller (GPMC) section in the device TRM.

6.4.5.14 HyperBus

The HyperBus module is a part of the device Flash Subsystem (FSS).

The HyperBus module is a low pin count memory interface that provides high read/write performance. The

HyperBus module connects to HyperBus memory (HyperFlash or HyperRAM) and uses simple HyperBus

protocol for read and write transactions.

There is one HyperBus™ module inside the device. The HyperBus module includes one HyperBus

Memory Controller (HBMC).

For more information, see HyperBus Interface section in the device TRM.

6.4.5.15 I2C

The device contains six multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an

interface between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via

the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8

bits of data to and from the LH device through the 2-wire I2C interface.

Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.

AM652X データシート(PDF) 248 Page - Texas Instruments

AM652X データシート(HTML) 248 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード