STPMIC1 datasheet(59/140 Pages) STMICROELECTRONICS

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Protection

level

LOCK_OCP

(NVM)

OCPOFF

[Rx] bit

STPMIC1 behavior

The STPMIC1 is kept forced in LOCK_OCP state (see Figure 53. STPMIC1 state

machine) until internal LOCK_OCP_FLAG is released by VIN_POR_Fall or optionally

by PONKEYn long key press, if enabled by setting PKEY_CLEAR_OCP_FLAG bit in

Table 31. PKEY_TURNOFF_CR register

5.4.8

BOOST overvoltage protection

See Section 4.5.1 Boost converter.

5.4.9

Watchdog feature

The STPMIC1 offers a watchdog mechanism that triggers a turn-OFF condition when the watchdog down counter

elapses.

Watchdog is disabled by default and it is enabled if WDG_ENA bit is set in Section 6.3.10 Watchdog control

The watchdog timer downcounter can be set in a range from 1 s to 256 s by 1 s step in Section 6.3.11 Watchdog

timer control register (WDG_TMR_CR).

Watchdog counter is reset by setting WDG_RST bit in Section 6.3.10 Watchdog control register (WDG_CR) and

when setting WDG_ENA from 0 to 1.

When enabled the watchdog timer remains active regardless MAIN or ALTERNATE mode. Watchdog is disabled

by reset, VIN_POR_Fall and turn-OFF.

5.5

Programming

5.5.1

I2C interface

I2C interface works in slave mode. It supports both standard and fast mode with data rate up to 400Kb/s. It

supports also fast mode plus (FM+) with data rate up to 1Mb/s that is suitable frequency for DVS operations.

Please refer to NXP UM10204 revision 5 for specifications.

SCL pin is the input clock used to shift data. SDA pin is the input/output bi-directional data.

Device ID

There is a device ID system to address the STPMIC1.

The address is stored into NVM_I2C_ADDR[6:0] bits in Section 6.7.8 NVM device address shadow register

(I2C_ADDR_SHR). Default address is 0x33.

Table 15. Device ID format

AdrID6

AdrID5

AdrID4

AdrID3

AdrID2

AdrID1

AdrID0

R/W

Read/write operation

Each transaction is composed of a start condition followed by a number of packet number (8-bit long)

representing either a device ID plus R/W command or register address or register data coming to/from slave

Table 15. Device ID format. An acknowledgment is needed after each packet. This acknowledgment is given

by the receiver of the packet. Transaction examples are given in Table 16. Register address format and

Table 17. Register data format. Multi read and multi write operations are supported.

Table 16. Register address format

RegADR7

RegADR6

RegADR5

RegADR4

RegADR3

RegADR2

RegADR1

RegADR0

STPMIC1

Programming

DS12792 - Rev 7

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