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STPMIC1 データシート(PDF) 104 Page - STMicroelectronics |
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STPMIC1 データシート(HTML) 104 Page - STMicroelectronics |
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104 / 140 page  6.5.6 Interrupt debug latch registers (INT_DBG_LATCH_Rx) Table 53. INT_DBG_LATCH_Rx Name Address 7 6 5 4 3 2 1 0 INT_DBG_ LATCH_R1 0x60 SWOUT _RI SWOUT _FA VBUS OTG_RI VBUS OTG_FA WKP _RI WKP _FA PKEY _RI PKEY _FA INT_DBG_ LATCH_R2 0x61 BST _OVP BST _OCP SWOUT _OCP VBUSOTG _OCP BUCK4_ OCP BUCK3_ OCP BUCK2_ OCP BUCK1_ OCP INT_DBG_ LATCH_R3 0x62 SWOUT_ SH VBUS OTG_SH LDO6_ OCP LDO5_ OCP LDO4_ OCP LDO3_ OCP LDO2_ OCP LDO1_ OCP INT_DBG_ LATCH_R4 0x63 SWIN _RI SWIN _FA reserved reserved VINLOW _RI VINLOW _FA THW_RI THW _FA Address: 0x60-0x63 Type: write register - read x00 Default: 0x00 Description: interrupt debug latch registers. Write registers only. Read always return 0x00. Writing 1 in the bit forces the corresponding interrupt event in INT_PENDING_Rx Refer to Section 6.5.2 Interrupt pending register 1 (INT_PENDING_R1), Section 6.5.3 Interrupt pending register 2 (INT_PENDING_R2), Section 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) and Section 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) about the interrupt description. STPMIC1 Interrupt registers DS12792 - Rev 7 page 104/140 |
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