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AD9546/PCBZ データシート(PDF) 28 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ データシート(HTML) 28 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 28 of 205
INVERSE USER TIME STAMPERS (IUTS) SPECIFICATIONS
Table 28.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FREQUENCY RANGE
0.001
2
200
kHz
IUTS frequency transport range for digitized clocking
PERIOD MONITOR THRESHOLD
±1.56
%
±2−6 relative to the average period IUTS transport
frequency
THROUGHPUT RATE
Data transfer involves a 14-byte block write to the IUTS
control registers followed by assertion of an IO update;
the indicated rate is the maximum continuous IUTS
traffic possible without causing IUTS invalidation; SPI
utilization other than for IUTS operation reduces
throughput
SCLK = 50 MHz
64
kSPS
20% SPI utilization allocation for IUTS operations
SCLK = 25 MHz
16
kSPS
10% SPI utilization allocation for IUTS operations
TIME OFFSET
Range
−29.8
+29.8
ns
Signed 24-bit range scaled by 2−48 sec
Resolution
3.55
fs
2−48 sec



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