AD9546SLASHPCBZ datasheet(64/205 Pages) AD

64 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 64 of 205

Guard Bypass Lock

The user has the option of preventing an unlock condition of

the common clock DPLL from triggering the synchronization

guard via the guard bypass lock bit, Bit 0 of Register 0x0D3C.

Logic 0 (default) allows an unlock condition to trigger the

synchronization guard. Logic 1 prevents an unlock condition

from triggering the synchronization guard.

Setting the guard bypass lock bit is useful when using the

digitized clock resources of the AD9546 in a nondigitized clock

application, for example, using two UTS resources to measure

the phase offset between two clock signals.

INITIAL SYNCHRONIZATION

The initial synchronization detect block ensures the CCS starts

in a known state. The CCS is not operational until the

synchronization detect block indicates initial synchronization

(the falling edge shown in Figure 51). Until initial

synchronization occurs, the initial synchronization detect block

holds the maximum magnitude detection block, the

synchronization offset refinement block, and the slew limiter in

a reset state. The initial synchronization detect block does not

indicate initial synchronization until the system clock PLL is

stable and a synchronization event occurs that does not trigger a

guard event (see the Synchronization Guard section).

READY STATUS

The CCS provides a status indicating that the common time

scale is ready to support digitized clocking resources. To check

the ready status of the CCS, use Bit 2 of Register 0x0D40, where

Logic 1 indicates the CCS is ready.

Ready status is also available via Bit 0 of Register 0x301D,

which is part of the IRQ mechanism (see the Interrupt Request

(IRQ) section) and through an appropriately configured Mx

status pin (see the Status and Control Pins section).

AD9546/PCBZ データシート(PDF) 64 Page - Analog Devices

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