AD9546SLASHPCBZ datasheet(191/205 Pages) AD

191 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 191 of 205

APPLICATIONS INFORMATION

DIGITIZED CLOCKING APPLICATION

The diagram in Figure 127 shows a simplified example of a

digitized clocking system. The system contains three digitized

clocking nodes, with one of the nodes functioning as the master

node and the other two nodes functioning as slave nodes (Slave

Node 0 and Slave Node 1). The master node receives a common

clock reference signal that serves as the common clock for the

entire system.

A reference clock can be applied at an input to one of the slave

nodes. The goal is to distribute the reference clock to each of

the nodes using data transport over a common digital

communication link rather than via analog clock signals. That

is, to transport the reference clock in frequency and phase from

the selected node to the other nodes over a data link rather than

routing the reference clock throughout the system in the form

of an analog signal. Digitized clocking technology enables this

ability to transport clock signals over a digital bus (see the

Digitized Clocking section for details).

The master node generates the common clock as a reference

clock to the slave nodes. The common clock is the time base

shared by all nodes, a fundamental digitized clocking

requirement. The master node also sends synchronization

information to the slave nodes. Synchronization comprises two

components: a physical synchronization event signal

(embedded within the common clock signal in Figure 127) and

a synchronizing code sent over the digital communication bus

(corresponding to the time associated with the synchronization

event signal). This two-pronged synchronization approach

results in all slave nodes sharing a common epoch with the

master node, with all nodes having a common (synchronized)

time scale.

For example, suppose the digitized clocking system has a

distributable reference clock applied to Slave Node 1. Slave

Node 1 digitizes the reference clock by creating time codes

(digital word representations of the reference clock rising

edges) derived from the common time scale. The time codes are

a proxy for the physical reference clock signal. Using digitized

clocking, Slave Node 1 sends the time codes to the master node

over the digital bus. Likewise, the master node distributes the

time codes to Slave Node 0 (and back to the Slave Node 1, if

required) over the same digital bus. Then, using digitized

clocking, the receiving nodes convert the time codes back into a

physical clock signal with the same frequency and phase as the

reference clock and aligned to within ±100 ps.

For digitized clocking applications, the recommendation is to

operate the AD9546 in SPI mode, rather than I2C mode,

because SPI supports a much higher serial transfer rate than I2C

(50 MHz for SPI vs. 400 kHz for I2C).

A key aspect of any synchronized clocking system is the timing

error caused by the propagation delay of clock signals sent

between the master and slave nodes. To properly align the

common time scale across all nodes, the system must measure

and compensate for the propagation delay between nodes. The

recommended method for quantifying the propagation delay is

measuring round trip delay in real time, which allows

continuous assessment and correction of delay that may arise

from temperature variations in the system. The AD9546 readily

accommodates assessment of round trip delay via its analog

loopback feature (see the Analog Clock Loopback section) and

time skew measurement processor (see the application example

in Figure 129 and the Clock Propagation Delay Measurement

section).

An example of a digitized clocking system appears in Figure 128,

which includes round trip delay measurement capability. The

example system comprises a timing card and a pair of line cards

interconnected via a backplane. The timing card and line cards

rely on digitized clocking to transport clock signals as time

codes via the AD9546 SPI port. Although not explicitly shown

in Figure 128, the AD9546 analog loopback feature for round

trip delay measurement requires the use of REFB or REFBB as

the loopback input and the M4 pin as the loopback return.

The timing card employs an IEEE 1588 servo for transporting

timing over ethernet (the traffic labels in the diagram). The

servo controls a PLL with the output of the PLL providing the

common clock for the system. The PLL produces three

identical clock signals with coincident output clock edges that

serve as the common clock input to each of the cards. This

arrangement, in combination with the AD9546 analog

loopback capability, allows the timing card to measure the

propagation delay between the timing card and each line card.

The measured propagation delay can then be compensated via

offsets applied to the digitized clocking paths.

The line cards handle Ethernet traffic via a physical layer (PHY)

with each line card serving multiple PHYs. Figure 128 shows

only one PHY with a connection to a UTS/IUTS pair on the

AD9546 for simplification. However, each PHY has access to a

dedicated UTS/IUTS pair on the AD9546. In this way, any one of

the PHYs can provide a received clock to the AD9546 for

digitization via a UTS. The digitized received clock is

transported over the digital bus to the timing card, where the

timing card uses the digitized receive clock as a SyncE clock for

the IEEE 1588 servo. The timing card, in turn, generates a

digitized clock for transport back to the line cards over the

digital bus. The line cards convert the digitized clock back to an

analog clock for use by the PHYs for clocking outgoing traffic.

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