MPC885ZP80 datasheet(4/87 Pages) NXP

4 / 87 page

MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7

Freescale Semiconductor

Features

— Periodic interrupt timer (PIT)

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE Std 1149.1™ test access port (JTAG)

•

Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,

IEEE Std 802.11i™, and iSCSI processing. Available on the MPC885, the security engine contains

a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:

— Data encryption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric key cipher

– ECB, CBC, and counter modes

– 128-, 192-, and 256- bit key lengths

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Crypto-channel supporting multi-command descriptor chains

— Integrated controller managing internal resources and bus mastering

— Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes

•

Interrupts

— Six external interrupt request (IRQ) lines

— 12 port pins with interrupt capability

— 23 internal interrupt sources

— Programmable priority between SCCs

— Programmable highest priority request

•

Communications processor module (CPM)

— RISC controller

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT

MODE

, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Several serial DMA (SDMA) channels to support the CPM

— Three parallel I/O registers with open-drain capability

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