IMX6SDLCEC datasheet(44/169 Pages) NXP

44 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.6.5

LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 27 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.

4.6.6

MLB I/O DC Parameters

The MLB interface complies with Analog Interface of 6-pin differential Media Local Bus specification

version 4.1. See 6-pin differential MLB specification v4.1, “MediaLB 6-pin interface Electrical

Characteristics” for details.

NOTE

The MLB 6-pin interface does not support speed mode 8192 fs.

Table 28 shows the Media Local Bus (MLB) I/O DC parameters.

4.7

I/O AC Parameters

This section includes the AC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

•

Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes

•LVDS I/O

•MLB I/O

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 5 and

Figure 6.

Table 27. LVDS I/O DC Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Differential Voltage

VOD

Rload-100

Ω Diff

250

350

450

Output High Voltage

VOH

IOH = 0 mA

1.25

1.375

1.6

Output Low Voltage

VOL

IOL = 0 mA

0.9

1.025

1.25

Offset Voltage

VOS

—

1.125

1.2

1.375

Table 28. MLB I/O DC Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Unit

Output Differential Voltage

VOD

Rload-50

Ω Diff

300

500

Output High Voltage

VOH

Rload-50

Ω Diff

1.25

1.75

Output Low Voltage

VOL

Rload-50

Ω Diff

0.75

1.25

Common-mode output voltage

((Vpadp*+Vpadn*)/2)

Vocm

Rload-50

Ω Diff

1.5

Differential output impedance

—

1.6

—

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