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IMX6SDLCEC データシート(PDF) 75 Page - NXP Semiconductors |
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IMX6SDLCEC データシート(HTML) 75 Page - NXP Semiconductors |
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75 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 75 4.11.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 51 shows the interface timing values. The number field in the table refers to timing signals found in Figure 38 and Figure 39. Table 51. Enhanced Serial Audio Interface (ESAI) Timing Parameters No. Characteristics1,2 Symbol Expression2 Min Max Condition3 Unit 62 Clock cycle4 tSSICC 4 × Tc 4 × Tc 30.0 30.0 — — i ck i ck ns 63 Clock high period: • For internal clock • For external clock — — 2 × Tc − 9.0 2 × Tc 6 15 — — — — ns 64 Clock low period: • For internal clock • For external clock — — 2 × Tc − 9.0 2 × Tc 6 15 — — — — ns 65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high — — — — — — 17.0 7.0 x ck i ck a ns 66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low — — — — — — 17.0 7.0 x ck i ck a ns 67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) high5 — — — — — — 19.0 9.0 x ck i ck a ns 68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low5 — — — — — — 19.0 9.0 x ck i ck a ns 69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high — — — — — — 16.0 6.0 x ck i ck a ns 70 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) low — — — — — — 17.0 7.0 x ck i ck a ns 71 Data in setup time before ESAI_RX_CLK (SCK in synchronous mode) falling edge — — — — 12.0 19.0 — — x ck i ck ns 72 Data in hold time after ESAI_RX_CLK falling edge — — — — 3.5 9.0 — — x ck i ck ns 73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK falling edge5 — — — — 2.0 12.0 — — x ck i ck a ns 74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK falling edge — — — — 2.0 12.0 — — x ck i ck a ns 75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling edge — — — — 2.5 8.5 — — x ck i ck a ns 78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high — — — — — — 18.0 8.0 x ck i ck ns 79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low — — — — — — 20.0 10.0 x ck i ck ns 80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) high5 — — — — — — 20.0 10.0 x ck i ck ns |
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