IMX6SDLCEC datasheet(73/169 Pages) NXP

73 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

4.11.2.1

ECSPI Master Mode Timing

Figure 36 depicts the timing of ECSPI in master mode. Table 49 lists the ECSPI master mode timing

characteristics.

Figure 36. ECSPI Master Mode Timing Diagram

Table 49. ECSPI Master Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

tclk

—ns

CS2

ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

tSW

21.5

—ns

CS3

ECSPIx_SCLK Rise or Fall1

1 See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”

tRISE/FALL

——

CS4

ECSPIx_SS_B pulse width

tCSLH

Half ECSPIx_SCLK period

—

CS5

ECSPIx_SS_B Lead Time (CS setup time)

tSCS

Half ECSPIx_SCLK period - 4

—

CS6

ECSPIx_SS_B Lag Time (CS hold time)

tHCS

Half ECSPIx_SCLK period - 2

—

CS7

ECSPIx_MOSI Propagation Delay (CLOAD =20pF)

tPDmosi

-1

CS8

ECSPIx_MISO Setup Time

•

tSmiso

—

CS9

ECSPIx_MISO Hold Time

tHmiso

0—

CS10 RDY to ECSPIx_SS_B Time2

2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

tSDRY

5—

CS7

CS2

CS4

CS6

CS5

CS8

CS9

ECSPIx_SCLK

ECSPIx_SS_B

ECSPIx_MOSI

ECSPIx_MISO

ECSPIx_RDY_B

CS10

CS3

CS1

Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be

connected between a single master and a single slave.

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