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IMX6SDLCEC データシート(PDF) 113 Page - NXP Semiconductors |
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IMX6SDLCEC データシート(HTML) 113 Page - NXP Semiconductors |
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113 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 113 4.11.13.5 Stream Transmission Mode Frame Transfer Figure 78. Stream Transmission Mode Frame Transfer (Synchronized Data Flow) 4.11.13.6 Frame Transmission Mode (Synchronized Data Flow) Figure 79. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow) 4.11.13.7 Frame Transmission Mode (Pipelined Data Flow) Figure 80. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow) 4.11.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load Table 72. DATA and FLAG Timing Parameter Description 1 Mbit/s 100 Mbit/s 200 Mbit/s tBit, nom Nominal bit time 1000 ns 10.0 ns 5.00 ns tRise, min and tFall, min Minimum allowed rise and fall time 2.00 ns 2.00 ns 1.00 ns tTxToRxSkew, maxfq Maximum skew between transmitter and receiver package pins 50.0 ns 0.5.0 ns 0.25 ns |
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