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MPC8560CPX667JC データシート(PDF) 28 Page - NXP Semiconductors

部品番号 MPC8560CPX667JC
部品情報  Integrated Processor Hardware Specifications
PDF  108 Pages
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メーカー  NXP [NXP Semiconductors]
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MPC8560CPX667JC データシート(HTML) 28 Page - NXP Semiconductors

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MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
28
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
7.2.2.2
MII Receive AC Timing Specifications
Table 24 provides the MII receive AC timing specifications.
Figure 11 shows the MII receive AC timing diagram.
Figure 11. MII Receive AC Timing Diagram
Table 24. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
3
—400
ns
RX_CLK clock period 100 Mbps
tMRX
—40
ns
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise and fall time
tMRXR, tMRXF
2,3
1.0
4.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to
the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing
(GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive
(RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data



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