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STM32F730Z8 データシート(PDF) 144 Page - STMicroelectronics |
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STM32F730Z8 データシート(HTML) 144 Page - STMicroelectronics |
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144 / 202 page  Electrical characteristics STM32F730x8 144/202 DS12536 Rev 2 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 41 or Figure 42, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176. When VREF- is not available, it is internally connected to VSSA. Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176. When VREF- is not available, it is internally connected to VSSA. STM32 1 μF // 10 nF 1 μF // 10 nF VREF+ (1) VDDA VSSA/VREF+ (1) ai17535c STM32F 1 μF // 10 nF ai17536c VREF+/VDDA VREF-/VSSA (1) (1) |
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