STM32WL55JC datasheet(29/147 Pages) STMICROELECTRONICS

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DS13293 Rev 2

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STM32WL55/54xx

Functional overview

nor an external super-capacitor are present. Three anti-tamper detection pins are available

in VBAT mode.

VBAT operation is automatically activated when VDD is not present.

An internal VBAT battery charging circuit is embedded and can be activated when VDD is

present.

Note:

When the microcontroller is supplied only from VBAT, external interrupts and RTC

alarm/events do not exit it from VBAT operation.

3.11

Low-power modes

The devices support several low-power modes to achieve the best compromise between

low-power consumption, short startup time, available peripherals and available wakeup

sources.

By default, the microcontroller is in Run mode, range 1, after a system or a power-on reset.

It is up to the user to select one of the low-power modes described below:

•

Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among

them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event

occurs.

•

Low-power run mode (LPRun): when the system clock frequency is reduced below

2 MHz. The code is executed from the SRAM or from the Flash memory. The regulator

is in low-power mode to minimize the operating current.

•

Low-power sleep mode (LPSleep): entered from the LPRun mode.

•

Stop 0 and Stop 1 modes: the content of SRAM1, SRAM2 and of all registers is

retained. All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are

disabled. LSI and LSE can be kept running.

RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz

radio may remain active independently from the CPUs.

Some peripherals with the wakeup capability can enable HSI16 RC during the Stop

mode to detect their wakeup condition.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption compared with Stop 2.

In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but

with much higher consumption. The active peripherals and wakeup sources are the

same as in Stop 1 mode that uses the low-power regulator.

The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz

or HSI16, depending on the software configuration.

•

Stop 2 mode: part of the VCORE domain is powered off. Only SRAM1, SRAM2, CPUs

and some peripherals preserve their contents (see Table 7).

All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.

LSI and LSE can be kept running.

RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The

sub-GHz radio may also remain active independent from the CPUs.

Some peripherals with the wakeup capability can enable HSI16 RC during the Stop 2

mode to detect their wakeup condition (see Table 7).

The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or

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