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FXLS8964AF データシート(PDF) 28 Page - NXP Semiconductors |
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FXLS8964AF データシート(HTML) 28 Page - NXP Semiconductors |
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28 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer Auto-increment Address Name Type Register Address F_READ = 0 F_READ = 1 Default Values BT_MODE = GND/[VDD] Comment VECM_MSB [1] [3] R 03h 04h/06h/08h/0Ch/0Eh/10h — 12-bit unsigned vector magnitude MSB/LSB: VECM[11:8] (MSB) when SENS_CONFIG2[LE_BE] = 0, and VECM[3:0] (LSB) when SENS_ CONFIG2[LE_BE] = 1. This register is skipped over by the auto-increment mechanism when SENS_ CONFIG5[VECM_EN] = 0. OUT_X_LSB [1] [3] R 04h 05h 06h/08h/00h — LSB/MSB of current 12-bit X-axis accelerometer output data – x_data_out[7:0] when SENS_ CONFIG2[LE_BE] = 0 and x_data_out[11:4] when SENS_CONFIG2[LE_BE] = 1. When SENS_ CONFIG5[X_DIS] = 1, this register is skipped over by the auto-increment mechanism. OUT_X_MSB [1] [3] R 05h 06h/08h/00h — MSB/LSB of current 12-bit X-axis accelerometer output data – x_data_out[11:8] when SENS_ CONFIG2[LE_BE] = 0 and x_data_out[3:0] when SENS_CONFIG2[LE_BE] = 1. When SENS_ CONFIG5[X_DIS] = 1, this register is skipped over by the auto-increment mechanism. OUT_Y_LSB [1] [3] R 06h 07h 08h/00h — LSB/MSB of current 12-bit Y-axis accelerometer output data – y_data_out[7:0] when SENS_ CONFIG2[LE_BE] = 0 and y_data_out[11:4] when SENS_CONFIG2[LE_BE] = 1. When SENS_ CONFIG5[Y_DIS] = 1, this register is skipped over by the auto-increment mechanism. OUT_Y_MSB [1] [3] R 07h 08h/00h — MSB/LSB of current 12-bit Y-axis accelerometer output data – y_data_out[11:8] when SENS_ CONFIG2[LE_BE] = 0 and y_data_out[3:0] when SENS_CONFIG2[LE_BE] = 1. When SENS_ CONFIG5[Y_DIS] = 1, this register is skipped over by the auto-increment mechanism. OUT_Z_LSB [1] [3] R 08h 09h 00h — LSB/MSB of current 12-bit Z-axis accelerometer output data – z_data_out[7:0] when SENS_ CONFIG5[LE_BE] = 0 and z_data_out[11:4] when SENS_CONFIG2[LE_BE] = 1. When SENS_ CONFIG5[Z_DIS] = 1, this register is skipped over by the auto-increment mechanism. OUT_Z_MSB [1] [3] R 09h 00h — MSB/LSB of current 12-bit Z-axis accelerometer output data – z_data_out[11:8] when SENS_ CONFIG2[LE_BE] = 0 and z_data_out[3:0] when SENS_CONFIG2[LE_BE] = 1. When SENS_ CONFIG5[Z_DIS] = 1, this register is skipped over by the auto-increment mechanism. Reserved registers RESERVED_REG1 — 0Ah 0Bh 00h Factory reserved register address 1 Output Buffer Configuration and Status BUF_STATUS[1][2] R 0Bh 0Ch/0Eh/10h 00h Buffer watermark and overflow status flags; stored sample count (buf_cnt[5:0]) BUF_X_LSB[1][3][4] R 0Ch 0Dh 0Eh/10h/0Ch — Head/Tail sample of output buffer X-axis LSB - buf_x_out[7:0] when SENS_CONFIG2[LE_BE] = 0 and buf_x_out[11:4] when SENS_CONFIG2[LE_BE] = 1. When SENS_CONFIG5[X_DIS] = 1, this register is skipped over by the auto-increment mechanism. BUF_X_MSB[1][3][4] R 0Dh 0Eh/10h/0Ch — Head/Tail sample of output buffer X-axis MSB - buf_x_out[11:8] when SENS_CONFIG2[LE_BE] = 0 and buf_x_out[3:0] when SENS_CONFIG2[ LE_BE ] = 1. When SENS_CONFIG5[X_DIS] = 1, this register is skipped over by the auto-increment mechanism. Table 20. Register address map...continued FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.4 — 7 December 2021 28 / 98 |
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