FXLS8964AF datasheet(45/98 Pages) NXP

45 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

Field

Description

2 to 1

FSR[1:0]

Full-scale measurement range (FSR) selection

00b: ±2 g; 0.98 mg/LSB (1024 LSB/g) nominal sensitivity

01b (default): ±4 g; 1.95 mg/LSB (512 LSB/g) nominal sensitivity

10b: ±8 g; 3.91 mg/LSB (256 LSB/g) nominal sensitivity

11b: ±16 g; 7.81 mg/LSB (128 LSB/g) nominal sensitivity

ACTIVE

Standby/Active mode selection

This bit selects between Standby mode and Active mode.

Note:

• When INT2_FUNC = 1, the Active bit becomes read only via the I2C or SPI interface as the INT2

pin logic state directly controls the device operating mode. The INT2_FUNC may only be enabled

(set to 1) when ACTIVE = 0. Similarly, the ACTIVE bit may only be set if INT2_FUNC = 0.

0: FXLS8964AF is placed in Standby mode and draws the minimum amount of current on the VDD pin

(IDD-STBY). Standby mode is the default mode after a POR or soft reset event.

1: FXLS8964AF is placed in Active mode and draws an IDD corresponding to the selected ODR in

HPM, the selected ODR in LPM, or the user-selected decimation and idle time settings in FPM.

Table 48. SENS_CONFIG1 register (address 15h) bit description...continued

15.12 SENS_CONFIG2 register (address 16h)

Bit

Name

WAKE_PM[1:0]

SLEEP_PM[1:0]

LE_BE

—

AINC_

TEMP

F_READ

Reset

Access

R/W

Table 49. SENS_CONFIG2 register (address 16h) bit allocation

Field

Description

7 to 6

WAKE_PM[1:0]

WAKE power mode selection

00b: Low-power mode is selected;

SENS_CONFIG3[7:4] bits are interpreted as WAKE_ODR[3:0]

and sets the ODR and decimation factor as per Table 52.

01b: High performance mode is selected;

SENS_CONFIG3[7:4] bits are interpreted as

WAKE_ODR[3:0] and set the ODR and decimation factor as per Table 53.

1xb: Flexible performance mode is selected;

SENS_CONFIG3[7:4] bits are interpreted as

WAKE_DEC[3:0], which sets the measurement decimation factor. The effective ODR (and

measurement current) is determined by the combination of the decimation factor and the 12-bit

measurement idle time programmed in the

WAKE_IDLE_MSB and WAKE_IDLE_LSB registers. See

Table 54 for the selectable decimation factors.

Note: In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only

the default LPM mode should be used.

Table 50. SENS_CONFIG2 register (address 16h) bit description

FXLS8964AF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.4 — 7 December 2021

45 / 98

FXLS8964AF データシート(PDF) 45 Page - NXP Semiconductors

FXLS8964AF データシート(HTML) 45 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

データシートダウンロード