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FW802B データシート(PDF) 20 Page - Agere Systems

部品番号 FW802B
部品情報  Low-Power PHY IEEE짰 1394A-2000 Two-Cable Transceiver/Arbiter Device
PDF  26 Pages
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メーカー  AGERE [Agere Systems]
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FW802B データシート(HTML) 20 Page - Agere Systems

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Agere Systems Inc.
Data Sheet, Rev. 3
May 2004
Two-Cable Transceiver/Arbiter Device
FW802B Low-Power PHY IEEE 1394A-2000
Internal Register Configuration
The PHY register map is shown below in Table 8. (Refer to IEEE 1394a-2000, 5B.1 for more information).
Table 8. PHY Register Map for the Cable Environment
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values
not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 9. PHY Register Fields for the Cable Environment
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
00002
Physical_ID
R
PS
00012
RHB
IBR
Gap_count
00102
Extended (7)
XXXXX
Total_ports
00112
Max_speed
XXXXX
Delay
01002
LCtrl
Contender
Jitter
Pwr_class
01012
Watchdog
ISBR
Loop
Pwr_fail
Timeout
Port_event Enab_accel Enab_multi
01102
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX
01112
Page_select
XXXXX
Port_select
10002
Register 0 Page_select
11112
Register 7 Page_select
REQUIRED
XXXXX RESERVED
Field
Size Type
Power Reset
Value
Description
Physical_ID
6
r
000000
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
R
1
r
0
When set to one, indicates that this node is the root.
PS
1
r
Cable power active.
RHB
1
rw
0
Root Hold-off Bit. When set to one, the force_root variable is
TRUE, which instructs the PHY to attempt to become the root dur-
ing the next tree identify process.
IBR
1
rw
0
Initiate Bus Reset. When set to one, instructs the PHY to set ibr
TRUE and reset_time to RESET_TIME. These values in turn
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166
µs. This bit is self-clearing.
Gap_count
6
rw
3F16
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of IEEE Standard 1394a-2000 for the encoding of this field.
Extended
3
r
7
This field has a constant value of seven, which indicates the
extended PHY register map.



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