FW802B datasheet(21/26 Pages) AGERE

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Agere Systems Inc.

Data Sheet, Rev. 3

May 2004

Two-Cable Transceiver/Arbiter Device

FW802B Low-Power PHY IEEE 1394A-2000

Internal Register Configuration (continued)

Table 9. PHY Register Fields for the Cable Environment (continued)

Field

Size Type Power Reset Value

Description

Total_ports

The number of ports implemented by this PHY. This count

reflects the number.

Max_speed

0102

Indicates the speed(s) this PHY supports:

0002 = 98.304 Mbits/s

0012 = 98.304 and 196.608 Mbits/s

0102 = 98.304, 196.608, and 393.216 Mbits/s

0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s

1002 = 98.304, 196.608, 393.216, 786.432, and

1,572.864 Mbits/s

1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and

3,145.728 Mbits/s

All other values are reserved for future definition.

Delay

0000

Worst-case repeater delay, expressed as 144 + (delay * 20) ns.

LCtrl

Link Active. Cleared or set by software to control the value of

the L bit transmitted in the node’s self-ID packet 0, which will be

the logical AND of this bit and LPS active.

Contender

See description.

Cleared or set by software to control the value of the C bit

transmitted in the self-ID packet. Powerup reset value is set by

C/LKON pin.

Jitter

000

The difference between the fastest and slowest repeater data

delay, expressed as (jitter + 1) * 20 ns.

Pwr_class

See description.

Power-Class. Controls the value of the pwr field transmitted in

the self-ID packet. See Section 4.3.4.1 of IEEE Standard

1394a-2000 for the encoding of this field. PC0, PC1, and PC2

pins set up power reset value.

Watchdog

When set to one, the PHY will set Port_event to one if resume

operations commence for any port.

ISBR

Initiate Short (Arbitrated) Bus Reset. A write of one to this bit

instructs the PHY to set ISBR true and reset_time to

SHORT_RESET_TIME. These values in turn cause the PHY to

arbitrate and issue a short bus reset. This bit is self-clearing.

Loop

Loop Detect. A write of one to this bit clears it to zero.

Pwr_fail

Cable Power Failure Detect. Set to one when the PS bit

changes from one to zero. A write of one to this bit clears it to

zero.

Timeout

Arbitration State Machine Timeout. A write of one to this bit

clears it to zero (see MAX_ARB_STATE_TIME).

Port_event

Port Event Detect. The PHY sets this bit to one if any of con-

nected, bias, disabled, or fault change for a port whose

Int_enable bit is one. The PHY also sets this bit to one if

resume operations commence for any port and Watchdog is

one. A write of one to this bit clears it to zero.

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