NM29N16 datasheet(3/30 Pages) NSC

3 / 30 page

Absolute Maximum Ratings

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Power Supply (VCC)

06V to 70V

Input Voltage (VIN)

06V to 70V

InputOutput Voltage (VIO)

06V to VCC g05V (s7V)

Power Dissipation (PD)

05W

Soldering Temperature (Tsolder) (10 seconds)

260 C

Storage Temperature (Tstg)

55 Cto150 C

Operating Temperature (Topr)0 Cto70 C

Recommended Operating

Conditions

Min

Typ

Max

Units

Power Supply (VCC)

High Level Input Voltage (VIH) 24

VCC a 05

Low Level Input Voltage (VIL) b03

2V (Pulse Width k 20 ns)

DC Operating Characteristics (TA e 0 Cto70 C VCC e 5V g10%)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ILI

Input Leakage Current

VIN e 0V to VCC

ILO

Output Leakage Current

VOUT e 04V to VCC

ICC01

Operating Current (Serial Read)

CE e VIL

tCYCLE e 80 ns

ICC02

Operating Current (Serial Read)

IOUT e 0mA

tCYCLE e 1 ms5

ICC03

Operating Current (Command Input)

tCYCLE e 80 ns

ICC04

Operating Current (Data Input)

tCYCLE e 80 ns

ICC05

Operating Current (Address Input)

tCYCLE e 80 ns

ICC06

Operating Current (Register Read)

tCYCLE e 80 ns

ICC07

Programming Current

ICC08

Erasing Current

ICCS1

Standby Current

CE e VIH

1mA

ICCS2

Standby Current

CE e VCC b 02V

100

VOH

High Level Output Voltage

IOH eb400 mA

VOL

Low Level Output Voltage

IOL e 21 mA

IOL(RB)

Output Current of (RB) Pin

VOL e 04V

Pin Functions

The NM29N16 is a sequential access memory which utilizes

time sharing input of address and data information

Command Latch Enable CLE

The CLE input signal is

used to control the input of commands into the internal

command register The command is latched into the com-

mand register from the IO port at the rising edge of the WE

signal while CLE is high

Address Latch Enable ALE

The ALE signal is used to

control the input of either address information or input data

into the internal addressdata register Address information

is latched at the rising edge of WE if ALE is high Input data

is latched if ALE is low

Chip Enable CE

The device goes into a low power stand-

by mode during a read operation when CE goes high The

CE signal is ignored when the device is in a busy state (RB

L) such as during a program or erase operation and will

not go into standby mode if a CE high signal is input

Write Enable

The WE signal is used to strobe data

into the IO port

Read Enable RE

The RE signal strobes data output Data

is available tREA after the falling edge of RE The internal

column address counter is also incremented (Address a 1)

with this falling edge

IO Port IO 1 – 8

The IO 1 – 8 pins are used as the port for

transferring address command and inputoutput data infor-

mation to or from the device

Write Protect

The WP signal is used to protect the

device from inadvertent programming or erasing The inter-

nal voltage regulator is reset when WP is low This signal is

usually used for protecting the data during the power onoff

sequence when the input signals are invalid

ReadyBusy RB

The RB output signal is used to indi-

cate the operating condition of the device The RB signal is

in a busy state (RB e L) during the program erase or read

operations and will return to a ready state (RB e H) after

completion The output buffer of this signal is an open drain

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