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UPSD3422 データシート(PDF) 80 Page - STMicroelectronics |
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UPSD3422 データシート(HTML) 80 Page - STMicroelectronics |
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80 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) I/O ports of mcu module UPSD3422, UPSD3433, UPSD3434, UPSD3454 80/300 CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All other types of reads to port SFRs will read the actual pin logic level and not the port latch. This is consistent with 8051 architecture. Figure 15. MCU module port pin function routing Figure 16. MCU I/O cell block diagram for port 1 8 P3 P1 P4 M C U A D GPIO (8) UART0 (2) Timer0/1 (4) I 2 C (2) GPIO (8) GPIO (8) Timer2 (2) UART1 (2) SPI (4) ADC (8) PCA (8) 8032 MCU CORE Low Addr & Data[7:0] 8 Hi Address [15:8] (Available on PSD module pins) MCU module 8 On 80-pin devices only Ports C N T L RD, WR, PSEN, ALE 4 SFR 8 8 SFR SFR SFR SFR SFR AI09199b P1.X Pin Analog_Alt_Func_En Analog_Pin_In Q D PRE SFR P1.X Latch 8032 Data Bus Bit GPIO P1.X SFR Write Latch MCU_Reset P1.X SFR Read Latch (for R-M-W instructions) P1.X SFR Read Pin Select_Alternate_Func Digital_Pin_Data_In IN 1 IN 0 Y MUX VCC VCC VCC SEL WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI09600 Obsolete Product(s) - Obsolete Product(s) |
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