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UPSD3422 データシート(PDF) 90 Page - STMicroelectronics |
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UPSD3422 データシート(HTML) 90 Page - STMicroelectronics |
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90 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) MCU bus interface UPSD3422, UPSD3433, UPSD3434, UPSD3454 90/300 Table 51. Number of MCU_CLK periods required to optimize bus transfer rate MCU clock frequency, MCU_CLK (fMCU) CW[1:0] Clk periods RDW[1:0] Clk periods WRW[1:0] Clk periods 3.3 V(1) 1. VDD of the PSD module. 5V(1) 3.3 V(1) 5V(1) 3.3 V(1) 5V(1) 40 MHz, Turbo mode PSD(2) 2. “Turbo mode PSD” means that the PSD module is in the faster, Turbo mode (default condition). A PSD module in Non-Turbo mode is slower, but consumes less current. See PSD module section, titled “PLD Non-Turbo mode” for details. 54 54 54 40 MHz, Non-turbo mode PSD 6 5 6 5 6 5 36 MHz, Turbo mode PSD 5 4 5 4 5 4 36 MHz, Non-turbo mode PSD 6 4 6 4 6 4 32 MHz, Turbo mode PSD 5 4 5 4 5 4 32 MHz, Non-turbo mode PSD 5 4 5 4 5 4 28 MHz, Turbo mode PSD 4 3 4 4 4 4 28 MHz, Non-turbo mode PSD 5 4 5 4 5 4 24MHz, Turbo mode PSD 43 44 44 24MHz, Non-turbo mode PSD 4 3 4 4 4 4 20 MHz and below, Turbo mode PSD 3 3 4 4 4 4 20 MHz and below, Non-turbo mode PSD 33 44 44 Obsolete Product(s) - Obsolete Product(s) |
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