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UPSD3422 データシート(PDF) 40 Page - STMicroelectronics |
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UPSD3422 データシート(HTML) 40 Page - STMicroelectronics |
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40 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) 8032 MCU registers UPSD3422, UPSD3433, UPSD3434, UPSD3454 40/300 7.7.5 Overflow flag (OV) The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL instruction results in an overflow (result greater than 255); a DIV instruction causes a divide- by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. The CLRV instruction will clear the OV flag at any time. 7.7.6 Parity flag (P) The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the sum is even. Figure 11. Program status word (PSW) register Table 4. Register bank select addresses RS1 RS0 Register bank 8032 internal data address 0 0 0 00h - 07h 0 1 1 08h - 0Fh 1 0 2 10h - 17h 1 1 3 18h - 1Fh AI06639 CY Reset Value 00h Parity Flag Bit not assigned Overflow Flag Register Bank Select Flags (to select Bank0-3) Carry Flag Auxillary Carry Flag General Purpose Flag AC FO RS1 RS0 OV P MSB LSB PSW Obsolete Product(s) - Obsolete Product(s) |
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