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CS5920 データシート(PDF) 49 Page - Applied Micro Circuits Corporation

部品番号 CS5920
部品情報  Full 132 Mbytes/sec Transfer Rate
PDF  160 Pages
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メーカー  AMCC [Applied Micro Circuits Corporation]
ホームページ  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

CS5920 データシート(HTML) 49 Page - Applied Micro Circuits Corporation

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S5920 – PCI Product
Revision 1.01 – November 28, 2005
AMCC Confidential and Proprietary
DS1596
49
Data Book
CACHE LINE SIZE REGISTER (CALN)
The cache line configuration register is used by bus
masters implementing memory write and invalidate
commands. The register defines the cache line size in
double word (64-bit) increments. The S5920 is a target
device not requiring cache. The register is hardwired
to 0.
Figure 13. Cache Line Size Register
Register Name:
Cache Line Size
Address Offset:
0Ch
Power-up value:
00h, hardwired
Boot-load:
not used
Attribute:
Read Only
Size:
8 bits
00h
0
7
Cache Line Size (RO)



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