CS5920 datasheet(70/160 Pages) AMCC

70 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

PCI INTERRUPT CONTROL/STATUS REG-

ISTER (INTCSR)

This register configures the conditions which will pro-

duce an interrupt on the PCI bus interface, a method

for viewing the cause of the interrupt, and a method for

acknowledging (removing) the interrupt’s assertion.

Interrupt sources:

•

The Outgoing mailbox becomes empty.

•

The Incoming mailbox becomes full.

•

Add-On interrupt pin enable and flag.

Figure 29. Interrupt Control Status Register

Interrupt Control and Status

PCI Address Offset:

38h

Power-up value:

00000C0Ch

PCI Attribute:

Read/Write, Read/Write Clear

Size:

32 bits

00000000

Interrupt Source (R/W)

Enable & Selection

D4 - D0 PCI Outgoing Mailbox

(Becomes Empty)

D4 = Enable Interrupt

D1 - D0 = Byte Number

00 = Byte 0

01 = Byte 1

10 = Byte 2

11 = Byte 3

0 0 0 X X 0 0 X X 1 1

000

X 1 1

432

Interrupt Asserted (RO)

Add-On Interrupt Pin

(ADDINT#) Status (RO)

Incoming Mailbox

Interrupt (R/WC)

Outgoing Mailbox

Interrupt (R/WC)

Add-On Interrupt Pin

(ADDINT#) Enable

(R/W)

D8 - D12 PCI Incoming Mailbox

D12 = Enable Interrupt

D9 - D8 = Byte Number

00 = Byte 0

01 = Byte 1

10 = Byte 2

11 = Byte 3

Interrupt Selection

Actual Interrupt

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