MPC5553 datasheet(11/60 Pages) FREESCALE

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Electrical Characteristics

MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

3.7

Power Up/Down Sequencing

Power sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is

required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this

power sequencing requirement, power up VRC33 within the specified operating range, even if not using

the on-chip voltage regulator controller. Refer to Section 3.7.1, “Power Up Sequence (If VRC33

Grounded)” and Section 3.7.2, “Power Down Sequence (If VRC33 Grounded).”

Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates,

so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, “Input

Value of Pins During POR Dependent on VDD33.”

Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the

VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV

or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33

leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on

the board power supply circuitry and the amount of board level capacitance.

Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large

increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this

increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are

even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD

to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently.

When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the

bypass capacitors internal and external to the device are already charged.

When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for

the VRC to operate within specification.

Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive

current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7

gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all

pins with pad type pad_mh (medium type) and pad_sh (slow type).

Table 7. Power Sequence Pin States (Fast Pads)

VDDE

VDD33

VDD

pad_fc (Fast)

Output Driver

State

Comment

LOW

Low

Functional I/O pins are clamped to VSS and VDDE

VDDE

LOW

High

VDDE

VDD33

LOW

High Impedance

POR asserted.

VDDE

VDD33

VDD

Functional

No POR asserted

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