MPC5553 datasheet(12/60 Pages) FREESCALE

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MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Electrical Characteristics

Freescale Semiconductor

3.7.1

Power Up Sequence (If VRC33 Grounded)

In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power

supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to

operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled,

the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since

they may negate as low as 2.0 V, it is necessary for VDD to be within spec before the 3.3-V POR and the

RESET POR negate.

Figure 2. Power Up Sequence if VRC33 Grounded

3.7.2

Power Down Sequence (If VRC33 Grounded)

In this case, the only requirement is that if VDD falls below its operating range, VDDSYN or the RESET

power must fall below 2.0 V before VDD is allowed to rise back into its operating range. This ensures that

digital 1.5-V logic that is only reset by ORed_POR, which may have been affected by the 1.5V supply

falling below spec, is reset properly.

3.7.3

Input Value of Pins During POR Dependent on VDD33

In order to avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not

treated as 1s when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6)

when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can

lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification.

VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33

lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag

requirements when powering down.

Table 8. Power Sequence Pin States (Medium and Slow Pads)

VDDEH

VDD

pad_mh/pad_sh

(Medium and Slow)

Output Driver

Comment

LOW

Low

Functional I/O pins are clamped to VSS and VDDEH

VDDEH

LOW

High Impedance

POR asserted

VDDEH

VDD

Functional

No POR asserted

VDDSYN and RESET Power

VDD

2.0V

1.35V

VDD must reach 1.35V before VDDSYN and the RESET power reach 2.0V

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