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M50FLW040A データシート(PDF) 8 Page - STMicroelectronics

部品番号 M50FLW040A
部品情報  4-Mbit (5 횞 64 Kbyte blocks 3 횞 16 횞 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
PDF  64 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M50FLW040A データシート(HTML) 8 Page - STMicroelectronics

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Summary description
M50FLW040A, M50FLW040B
8/64
Figure 1.
Logic diagram (FWH/LPC interface)
1.
ID3 is Reserved for Future Use (RFU) in LPC mode.
Table 1.
Signal names (FWH/LPC Interface)
FWH0/LAD0-FWH3/LAD3
Input/Output Communications
FWH4/LFRAME
Input Communication Frame
ID0-ID3
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave disconnected
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast Program and Erase Operations
VSS
Ground
NC
Not Connected Internally
AI08417B
4
FWH4/LFRAME
FWH0/LAD0
FWH3/LAD3
VCC
M50FLW040A
M50FLW040B
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID31
GPI0-GPI4
VPP



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