RT9758 datasheet(32/61 Pages) RICHTEK

32 / 61 page

RT9758

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS9758-03

May 2023

Bit

Bit Name

Default

WDT

RST

REG

RST

Type

Description

7:6

CFLY_DIAG_

TIME

Program pre-charge timing of CFLY in DIV2

mode or reverse DIV2 mode.

In DIV2 mode, pre-charge timing of CFLY is

sum of CFLY_DIAG_TIME and

VOUT_ERR_ON_TIME.

In reverse DIV2 mode, pre-charge timing of

CFLY is depend on CFLY_DIAG_TIME.

00 : 0.5ms

01 : 1ms

10 : 2ms (default)

11 : 4ms

5:4

PRECHARGE

_CURRENT

Program VOUT or CFLY pre-charge current

in soft-start period.

00 : Reserved

01 : 330mA

10 : 500mA (default)

11 : 660mA

3:2

VOUT_ERR_

ON_TIME

Program pre-charge timing of VOUT in

bypass mode and DIV2 mode.

In DIV2 mode, pre-charge timing of VOUT is

sum of CFLY_DIAG_TIME and

VOUT_ERR_ON_TIME.

In bypass mode, pre-charge timing of VOUT

is depend on VOUT_ERR_ON_TIM.

00 : 0.5ms

01 : 1ms

10 : 2ms (default)

11 : 4ms

VOUT_ERR_

OFF_TIME

Program a turn off timing after VOUT_ERR is

triggered in bypass mode.

0 : 40ms (default)

1 : 80ms

BEHAVIOR_

AFTER_WDT

Select the converter behavior of converter

after trigger watchdog timeout event.

0 : Converter would enter standby mode and

Q0_CONTROL set to 00 after WDT is

triggered

1 : Only when in bypass mode, the converter

would keep the same mode as before, after

WDT is triggered. (default)

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