RT9758 datasheet(51/61 Pages) RICHTEK

51 / 61 page

RT9758

is a registered trademark of Richtek Technology Corporation.

DS9758-03

May 2023

www.richtek.com

Parallel Application

For higher charging current application, it is available to use two RT9758 in parallel architecture. The advantages of

using parallel architecture are reducing cable losses, improve efficiency of charge system and cut down charging

period. The high power solution that uses two RT9758 is shown in Figure 13. The slave address of RT9758 can be

configured by setting ADDR pin while device power up. In order to avoid unstable ripple issue while charging with

parallel architecture, the RT9758 is established with synchronization function at SYNC pin. If the RT9758 is

configured to master mode (SYNC_SLAVE_EN bit = 1) and synchronization function is active (SYNC_FUNCTION_

EN bit = 1), the SYNC pin provides synchronization pulses with frequency equal to twice switching frequency and

50% duty cycle. If the RT9758 is configured to slave mode (SYNC_SLAVE_EN bit = 0) and synchronization function

is active (SYNC_FUNCTION_EN bit = 1), the device works only while SYNC pin receive synchronization pulses. For

using the synchronization function, the SYNC pins of the two devices should be connected to each other. The

configuration mode and synchronization function can be configured by 0x0D[3] bit and 0x0D[2] bit, respectively.

RT9758

VBUS

SDA

SCL

INT

CFH2

CFL2

PGND

VOUT

WRX_OK

WRX_IN

CFH1

CFL1

Host

Pull Up

CVBUS1

CFLY3

CFLY1

A6, B6, E6, F6

A4, B4, C4,

D4, E4, F4

E5,F5

A5,B5

A3,B3

E3,F3

C1,D1

A2,B2,C2,

D2,E2,F2

SYNC

CFLY2

CFLY4

COUT1

ADDR

VBUS

AGND

BST1

BST2

CB1

CB2

WRX_IN

CVBUS2

VADDR1

22µF

22nF

22µF

4.7µF

CWRX1

2.2µF

10k

RT9758

VBUS

SDA

SCL

INT

CFH2

CFL2

PGND

VOUT

WRX_OK

WRX_IN

CFH1

CFL1

CVBUS3

CFLY7

CFLY5

A6, B6, E6, F6

A4, B4, C4,

D4, E4, F4

E5,F5

A5,B5

A3,B3

E3,F3

C1,D1

A2,B2,C2,

D2,E2,F2

SYNC

CFLY6

CFLY8

COUT2

ADDR

AGND

BST1

BST2

CB3

CB4

CVBUS4

VADDR2

22µF

22nF

22µF

4.7µF

CWRX2

2.2µF

VOUT

Master

Slave

Figure 13. Parallel Application Circuit

In DIV2 mode and reverse DIV2 mode, all of phase angle in the device need to be defined correctly for optimize

output ripple and charging efficiency, especially parallel application. The Table 10 shows the recommended phase

angle in 4 operation modes with different configuration. For example, in DIV2 mode parallel application, the A phase

between master and slave device should be shift 90 degrees, the A and B phase in the same device should be shift

180 degrees. It is strongly prohibited to change PHASE_A_ANGLE bit and PHASE_B_ANGLE bit during charging.

If parallel architecture is used, the start-up sequence should be compiled with the rules below. The RT9758 set as

slave (RT9758_S) should be enabled before host enables the RT9758 set as master (RT9758_M) in order to achieve

parallel application. The RT9758_S will not switch until the SYNC pin receives synchronization pulses provided by

the RT9758_M. The communication flow between smart wall adapter, wireless power device and parallel charge

system is shown in Figure 14.

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