M65KA128AL datasheet(14/53 Pages) STMICROELECTRONICS

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Operations

M65KA128AL

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3.7

Deep Power-Down

The purpose of this mode is to achieve maximum power reduction by cutting the power

supply to the whole memory array. Data is no longer retained when the device enters Deep

Power-Down Mode.

The Low Power SDRAM is switched to Deep Power-Down mode by applying VIL to E and W,

and VIH to RAS and CAS on the rising edge of the clock, K, and by driving KE Low, VIL. For

more information, see Figure 25: Deep Power-Down Entry AC Waveforms.

The Low Power SDRAM is released from Deep Power-Down mode by applying VIH to KE,

with all other pins Don’t Care. Then a special sequence, is required before the device can

take any new command into account:

Maintain No Operation status conditions (see Table 3 for a minimum time of 200µs,

Issue a Precharge command to all the banks of the device (see Section 4.6: Precharge

command for details),

Issue 2 or more Auto-Refresh commands,

Issue a Mode Register Set command and an Extended Mode Register Set command to

initialize the Mode Register and the Extended Mode Register, respectively.

The third and fourth steps can be swapped.

The Deep Power-Down mode exit sequence is illustrated in Figure 26: Deep Power-Down

Exit AC Waveforms.

Table 2.

Operating Modes (1)

Operating Mode

KEn-1

KEn

RAS

CAS

A10

A9, A11

A0-A7

BA0-BA1

Burst Read

VIH

XVIL

VIH

VIL

VIH

VIL

Valid

Start

Column

Address

Bank Select

Burst Write

VIH

XVIL

VIH

VIL

Valid

Start

Column

Address

Bank Select

Self Refresh

VIH

VIL

VIH

Auto Refresh

VIH

VIL

VIH

Power-Down

VIH

VIL

VIH

Deep Power-Down

VIH

VIL

VIH

VIL

Device Deselect

VIH

XVIH

No Operation

VIH

XVIL

VIH

X = Don’t Care VIL or VIH.

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