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AM29BDD160G データシート(PDF) 70 Page - Advanced Micro Devices

部品番号 AM29BDD160G
部品情報  16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
PDF  79 Pages
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDD160G データシート(HTML) 70 Page - Advanced Micro Devices

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Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 26.
DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
Status Data
VA
VA
tOE
tOE
1.
The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,
the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one
clock cycle before data.
4. Data polling requires burst access time delay.
Figure 27.Synchronous Data Polling Timing/Toggle Bit Timings



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