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AM29PDL128G35PEFN データシート(PDF) 44 Page - Advanced Micro Devices

部品番号 AM29PDL128G35PEFN
部品情報  128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOTM Control
PDF  71 Pages
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29PDL128G35PEFN データシート(HTML) 44 Page - Advanced Micro Devices

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October 28, 2004
Am29PDL128G
43
P R E L IM IN A R Y
Legend:
DYB = Dynamic Protection Bit
SSA = SecSi Sector Address (A6:A0) is (0011010).
PD[1:0] = Program Data. Password written in 2 portions.
PPB = Persistent Protection Bit
PWA = Password Address. A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock bit status.
SA = Sector Address where security command applies. Address bits
A21:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010) (Note 16)
EP = PPB Erase Address (A6:A0) is (1111010) (Note 16)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1.
See Table 1 for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells in the able denote read cycles. All other cycles are
write operations.
4.
During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in the table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
5.
Reset command returns device to reading array.
6.
Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate
bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle
6, entire command sequence must be issued and verified again.
7.
Data is latched on rising edge of WE#.
8.
Entire command sequence must be executed for each portion of
password.
9.
Command sequence returns FFh if PPMLB is set.
10. Password is written over four consecutive cycles at addresses
0-3.
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command
sequence must be issued and verified again. Before issuing erase
command, all PPBs should be programmed to prevent PPBs
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. For all other parts that use the Persistent Protection Bit (excluding
PDL640G), the WP address is 00000010 and the EP address is
01000010.
Table 15.
Sector Protection Command Definitions (x32 Mode)
Command (Notes)
Bus Cycles (Notes 1, 2, 3, and 4)
Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
1
XXX
F0
SecSi Sector Entry
3
555
AA
2AA
55
(BA)555
88
SecSi Sector Exit
4
555
AA
2AA
55
(BA)555
90
XX
00
SecSi Protection Bit Program (5, 6)
6
555
AA
2AA
55
(BA)555
60
SSA
68
SSA
48
XX
RD(0)
Password Program (5, 7, 8)
4
555
AA
2AA
55
555
38
XX[0-1]
PD[0-1]
Password Verify (8, 9)
4
555
AA
2AA
55
555
C8
PWA[0-1]
PWD[0-1]
Password Unlock (7, 10, 11)
4
555
AA
2AA
55
555
28
PWA[0-1]
PWD[0-1]
PPB Program (6, 12)
6
555
AA
2AA
55
555
60
(SA)WP
68
(SA)WP
48
(SA)WP RD(0)
All PPB Erase (13, 14)
6
555
AA
2AA
55
555
60
(SA)EP
60
(SA)EP
40
(SA)WP RD(0)
PPB Lock Bit Set
3
555
AA
2AA
55
555
78
PPB Lock Bit Status (15)
4
555
AA
2AA
55
555
58
SA
RD(1)
DYB Write (7)
4
555
AA
2AA
55
555
48
SA
X1
DYB Erase (7)
4
555
AA
2AA
55
555
48
SA
X0
DYB or PPB Status
4
555
AA
2AA
55
555
58
SA
RD(0)
PPMLB Program (6, 12)
6
555
AA
2AA
55
555
60
PL
68
PL
48
XX
RD(0)
PPMLB Status (5)
4
555
AA
2AA
55
555
60
PL
RD(0)
SPMLB Program (6, 12)
6
555
AA
2AA
55
555
60
SL
68
SL
48
XX
RD(0)
SPMLB Status (5)
4
555
AA
2AA
55
555
60
SL
RD(0)



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