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AM29PDL128G35PEFN データシート(PDF) 67 Page - Advanced Micro Devices

部品番号 AM29PDL128G35PEFN
部品情報  128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOTM Control
PDF  71 Pages
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29PDL128G35PEFN データシート(HTML) 67 Page - Advanced Micro Devices

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Am29PDL128G
October 28, 2004
P R E L IM IN A R Y
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°C, 3.0 V V
CC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°C, V
CC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See Tables 14, 15, 16, and 17 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except V
CC. Test conditions: VCC = 3.0 V, one pin at a time.
BGA BALL CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
100
sec
Double Word Program Time
16.6
330
µs
Excludes system level
overhead (Note 5)
Word Program Time
12.6
210
µs
Accelerated Double Word Program Time
14.5
240
µs
Accelerated Word Program Time
10.5
120
µs
Chip Program Time
(Note 3)
Double Word Mode
69.6
208
sec
Word Mode
105.7
317
Description
Min
Max
Input voltage with respect to V
SS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
13 V
Input voltage with respect to V
SS on all I/O pins
–1.0 V
V
CC + 1.0 V
V
CC Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN = 0
4.2
5.0
pF
C
OUT
Output Capacitance
V
OUT = 0
5.4
6.5
pF
C
IN2
Control Pin Capacitance
V
IN = 0
3.9
4.7
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°C10
Years
125
°C20
Years



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