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IMX7DCEC データシート(PDF) 29 Page - NXP Semiconductors |
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IMX7DCEC データシート(HTML) 29 Page - NXP Semiconductors |
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29 / 161 page  Electrical characteristics i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023 NXP Semiconductors 29 The valid power mode transition is shown in this diagram. Figure 3. i.MX 7Dual Power Modes The power mode transition condition is defined in the following table. The following table summarizes the external power supply state in all the power modes. Table 13. Power Mode Transition Transition From To Condition 1 OFF RUN VDD_SVNS_IN supply present. 2 SNVS OFF VDD_SNVS_IN supply removal. 3 RUN SNVS ONOFF long press, or SW. 4 SNVS RUN ONOFF press, or RTC, or tamper event. 5 RUN LPSR SW. 6 LPSR RUN ONOFF press, or RTC, or tamper event, or GPIO event. 7 RUN Low Power SW (CPU execute WFI) 8 Low Power RUN RTC, tamper event, IRQ. Table 14. Power modes Power rail OFF SVNS LPSR RUN Low Power VDD_ARM OFF OFF OFF ON ON/ OFF VDD_SOC OFF OFF OFF ON ON VDDA_1P8_IN OFF OFF OFF ON ON VDD_SNVS_IN OFF ON ON ON ON VDD_LPSR_IN OFF OFF ON ON ON NVCC_GPIO1/2 OFF OFF ON ON ON NVCC_DRAM OFF OFF OFF ON ON OFF RUN SNVS LPSR Low Power 1 2 3 4 5 6 7 8 |
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