IMX7DCEC datasheet(39/161 Pages) NXP

部品番号	IMX7DCEC

部品情報	i.MX 7Dual Family of Applications Processors Datasheet

PDF	161 Pages

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メーカー	NXP [NXP Semiconductors]

ホームページ	http://www.nxp.com

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39 / 161 page

Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Figure 4. i.MX 7Dual power-up sequence

4.1.10 Power-down sequence

The i.MX7 processors have the following power-down sequence requirements:

• VDD_SNVS _IN to be turned off last after any other power supply.

• NVCC_DRAM/NVCC_DRAM_CKE to be turned off before VDD_SOC.

• There are no special timing requirements forVDD_USB_OTG1_3P3_IN

andVDD_USB_OTG2_3P3_IN.

The power-down sequence is shown in Figure 5 with the following timing parameters:

Time from first power rails (except SNVS) to ramp down to all the power rails (except

SNVS) get to ground, minimal delay is 0ms, no max delay requirement.

Time from all the power rails power down (except SNVS) to SVNS power down,

minimal delay is 0ms, no max delay requirement.

Time from NVCC_DRAM/NVCC_DRAM_CKE power down to VDD_SOC power

down, minimal delay is 0ms, no max delay requirement.

IMX7DCEC データシート(PDF) 39 Page - NXP Semiconductors