PM7346 datasheet(60/419 Pages) PMC

60 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 39

Pin Name

Type

Pin No.

Function

RGAPCLK[4]

RGAPCLK[3]

RGAPCLK[2]

RGAPCLK[1]

Output

W13

U10

Framer Recovered Gapped Clock

(RGAPCLK[4:1]). RGAPCLK[4:1] is valid

when the S/UNI-QJET is configured as a

DS3, E3, or J2 framer for non-ATM

applications by setting the FRMRONLY bit

in the S/UNI-QJET Configuration 1

S/UNI-QJET Configuration 2 Register.

RGAPCLK[4:1] is the recovered clock and

timing reference for RDATO[4:1].

RGAPCLK[4:1] is held high for bit

positions which correspond to overhead.

LCD[4]

LCD[3]

LCD[2]

LCD[1]

Output

Y14

W10

Loss of Cell Delineation (LCD[4:1]).

LCD[4:1] is an active high signal which is

asserted while the ATM cell processor has

detected a Loss of Cell Delineation defect.

The FRMRONLY bit in the S/UNI-QJET

Configuration 1 Register must be set to

logic 0 for LCD[4:1] to be valid.

RDATO[4]

RDATO[3]

RDATO[2]

RDATO[1]

Framer Receive Data (RDATO[4:1]).

RDATO[4:1] is valid when the S/UNI-QJET

is configured as a DS3, E3, or J2 framer

for non-ATM applications by setting the

FRMRONLY bit in the S/UNI-QJET

Configuration 1 Register.

RDATO[4:1] is the received data aligned to

RFPO/RMFPO[4:1] and ROVRHD[4:1].

RDATO[4:1] is updated on the active edge

(as set by the RSCLKR register bit) of

RSCLK[4:1] or RGAPCLK[4:1].

PM7346 データシート(PDF) 60 Page - PMC-Sierra, Inc

PM7346 データシート(HTML) 60 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード