PM7347 datasheet(66/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1

bits or any user programmable bit pattern from 1 to 32 bits in length. The PRGD can also insert

single bit errors or a bit error rate between 10-1 to 10-7.

The PRGD can be programmed to check for the presence of the generated pseudo-random

pattern. The PRGD can perform an auto-synchronization to the expected pattern, and generate

interrupts on detection and loss of the specified pattern. The PRGD can accumulate the total

number of bits received and the total number of bit errors in two saturating 32-bit counters. The

counters accumulate over an interval defined by writes to the S/UNI-JET Identification/Master

Reset, and Global Monitor Update Register (006H) or by writes to any PRGD accumulation

and the counters reset to begin accumulating for the next interval. The counters are reset in such a

way that no events are missed. The data is then available in the holding registers until the next

accumulation. In addition to the two counters, a record of the 32 bits received immediately prior

to the accumulation is available.

The PRGD may also be programmed to check for repetitive sequences. When configured to

detect a pattern of length N bits, the PRGD will load N bits from the detected stream, and

determine whether the received pattern repeats itself every N subsequent bits. Should it fail to

find such a pattern, it will continue loading and checking until it finds a repetitive pattern. All the

features (error counting, auto-synchronization, etc.) available for pseudo-random sequences are

also available for repetitive sequences. Whenever a PRGD accumulation is forced, the PRGD

stores a snapshot of the 32 bits received immediately prior to the accumulation. This snapshot

may be examined in order to determine the exact nature of the repetitive pattern received by

PRGD.

The pseudo-random or repetitive pattern can be inserted/extracted in the PLCP payload (if PLCP

framing is enabled) or in the DS3, E3, J2, or Arbitrary framing format payload (if PLCP framing

is disabled). It cannot be inserted into the ATM cell payload.

10.10 RXCP-50 Receive Cell Processor

The Receive Cell Processor (RXCP-50) Block integrates circuitry to support:

• Scrambled or unscrambled cell payloads.

• Scrambled or unscrambled cell headers.

• HCS verification.

• Idle cell filtering.

• Performance monitoring.

The RXCP-50 operates upon a delineated cell stream. For PLCP based transmissions systems,

cell delineation is performed by the SPLR. For non-PLCP based transmission systems, cell

delineation is performed by the ATMF. Framing status indications from these blocks ensure that

cells are not written to the RXFF while the SPLR is in the LOF state, or cells are not written to

the RXFF while the ATMF is in the HUNT or PRESYNC states.

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