PM7347 datasheet(69/341 Pages) PMC

69 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

• Filling the receive FIFO.

• Indicating when the receive FIFO contains cells.

• Maintaining the receive FIFO read and write pointers.

• Detecting FIFO overrun and underrun conditions.

The FIFO interface is “UTOPIA Level 2"-compliant. It accepts a read clock (RFCLK) and read

enable signal (RENB). The receive FIFO output bus (RDAT[15:0]) is tri-stated when RENB is

logic one or if the PHY device address (RADR[4:0]) selected does not match this device's

address. The interface indicates the start of a cell (RSOC) and the receive cell available status

(RCA and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges of

RFCLK). The RCA (and DRCA[x]) status changes from available to unavailable when the FIFO

is either empty (RCALEVEL0=1) or near empty (RCALEVEL0 is logic zero).

The interface also indicates FIFO overruns via a maskable interrupt and register bits. Read

accesses while RCA (or DRCA[x]) is a logic zero will output invalid data.

10.12 CPPM Cell and PLCP Performance Monitor

The Cell and PLCP Performance Monitor (CPPM) Block interfaces directly to the SPLR to

accumulate bit interleaved parity error events, framing octet error events, and FEBE events in

saturating counters. When the PLCP framer (SPLR) declares LOF, the following are not counted:

bit interleaved parity error events, framing octet error events, FEBE events, HCS error events.

When an accumulation interval is signaled by a write to the CPPM register address space or to the

S/UNI-JET Identification, Master Reset, and Global Monitor Update Register, the CPPM

transfers the current counter values into holding registers and resets the counters to begin

accumulating error events for the next interval. The counters are reset in such a manner that error

events occurring during the reset period are not missed.

10.13 DS3 Transmitter

The DS3 Transmitter (T3-TRAN) Block integrates circuitry required to insert the overhead bits

into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible

with the M23 and C-bit parity DS3 formats.

Status signals such as far end receive failure (FERF), the AIS, and the idle signal can be inserted

when their transmission is enabled by internal register bits. FERF can also be automatically

inserted on detection of any combination of LOS, OOF or RED, or AIS by the T3-FRMR.

A valid pair of P-bits is automatically calculated and inserted by the T3-TRAN. When C-bit

parity mode is selected, the path parity bits, and FEBE indications are automatically inserted.

When enabled for C-bit parity operation, the FEAC channel is sourced by the XBOC bit-oriented

code transmitter. The PMDLmessages are sourced by the TDPR data link transmitter. These

overhead signals can also be overwritten by using the TOH[x] and TOHINS[x] inputs.

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